View MCP621T-EMF_4571158.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MCP621/2/5
20 MHz, 2.5 mA Op Amps with mCal
Features
* * * * * * * * * Gain Bandwidth Product: 20 MHz (typical) Short Circuit Current: 70 mA (typical) Noise: 13 nV/Hz (typical, at 1 MHz) Calibrated Input Offset: 200 V (maximum) Rail-to-Rail Output Slew Rate: 10 V/s (typical) Supply Current: 2.5 mA (typical) Power Supply: 2.5V to 5.5V Extended Temperature Range: -40C to +125C
Description
The Microchip Technology, Inc. MCP621/2/5 family of operational amplifiers features low offset. At power up, these op amps are self-calibrated using mCal. Some package options also provide a calibration/chip select pin (CAL/CS) that supports a low power mode of operation, with offset calibration at the time normal operation is re-started. These amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. This family is offered in single with CAL/CS pin (MCP621), dual (MCP622) and dual with CAL/CS pins (MCP625). All devices are fully specified from -40C to +125C.
Typical Applications
* * * * Driving A/D Converters Power Amplifier Control Loops Barcode Scanners Optical Detector Amplifier
Typical Application Circuit
VDD/2 VIN R1 R3 R2 VOUT MCP62X RL
Design Aids
* * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes
Power Driver with High Gain
Package Types
MCP621 SOIC
NC 1 VIN- 2 VIN+ 3 VSS 4 8 CAL/CS 7 VDD 6 VOUT 5 VCAL
MCP622 3x3 DFN *
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 EP 9 8 VDD 7 VOUTB 6 VINB- 5 VINB+
MCP625 3x3 DFN *
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 CALA/CSA 5 EP 11 10 VDD 9 VOUTB 8 VINB- 7 VINB+ 6 CALB/CSB
MCP622 SOIC
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB 6 VINB- 5 VINB+
MCP625 MSOP
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 CALA/CSA 5 10 VDD 9 VOUTB 8 VINB- 7 VINB+ 6 CALB/CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
(c) 2009 Microchip Technology Inc.
DS22188A-page 1
MCP621/2/5
NOTES:
DS22188A-page 2
(c) 2009 Microchip Technology Inc.
MCP621/2/5
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.2.2 "Input Voltage and Current Limits".
VDD - VSS .......................................................................6.5V Current at Input Pins ....................................................2 mA Analog Inputs (VIN+ and VIN-) . VSS - 1.0V to VDD + 1.0V All other Inputs and Outputs .......... VSS - 0.3V to VDD + 0.3V Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ..........................150 mA Storage Temperature ...................................-65C to +150C Max. Junction Temperature ........................................ +150C ESD protection on all pins (HBM, MM) ................ 1 kV, 200V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Input Offset Input Offset Voltage Input Offset Voltage Trim Step Size Input Offset Voltage Drift Power Supply Rejection Ratio Input Current and Impedance Input Bias Current Across Temperature Across Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common-Mode Input Voltage Range Common-Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing
Sym
VOS VOSTRM VOS/TA PSRR IB IB IB IOS ZCM ZDIFF VCMR CMRR CMRR AOL AOL VOL, VOH VOL, VOH
Min
-200 -- -- 61 -- -- -- -- -- -- VSS - 0.3 65 68 88 94 VSS + 20 VSS + 40 40 35
Typ
-- 37 2.0 76 5 100 1700 10 1013||9 1013||2 -- 81 84 117 126 -- -- 85 70
Max
+200 200 -- -- -- -- 5,000 -- -- -- VDD - 1.3 -- -- -- -- VDD - 20 VDD - 40 130 110
Units
V V dB pA pA pA pA ||pF ||pF V dB dB dB dB mV mV mA mA (Note 3)
Conditions
After calibration (Note 1) (Note 2)
V/C TA= -40C to +125C
TA= +85C TA= +125C
VDD = 2.5V, VCM = -0.3 to 1.2V VDD = 5.5V, VCM = -0.3 to 4.2V VDD = 2.5V, VOUT = 0.3V to 2.2V VDD = 5.5V, VOUT = 0.3V to 5.2V VDD = 2.5V, G = +2, 0.5V Input Overdrive VDD = 5.5V, G = +2, 0.5V Input Overdrive VDD = 2.5V (Note 4) VDD = 5.5V (Note 4)
Output Short Circuit Current Note 1: 2: 3: 4:
ISC ISC
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included. Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability. See Figure 2-6 and Figure 2-7 for temperature effects. The ISC specifications are for design guidance only; they are not tested.
(c) 2009 Microchip Technology Inc.
DS22188A-page 3
MCP621/2/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Calibration Input Calibration Input Voltage Range Internal Calibration Voltage Input Impedance Power Supply Supply Voltage Quiescent Current per Amplifier POR Input Threshold, Low POR Input Threshold, High Note 1: 2: 3: 4:
Sym
VCALRNG VCAL ZCAL VDD IQ VPRL VPRH
Min
VSS + 0.1 0.323VDD -- 2.5 1.2 1.15 --
Typ
-- 0.333VDD 100 || 5 -- 2.5 1.40 1.40
Max
VDD - 1.4 0.343VDD -- 5.5 3.6 -- 1.65
Units
mV k||pF V mA V V IO = 0
Conditions
VCAL pin externally driven VCAL pin open
Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included. Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability. See Figure 2-6 and Figure 2-7 for temperature effects. The ISC specifications are for design guidance only; they are not tested.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-2).
Parameters
AC Response Gain Bandwidth Product Phase Margin Open-Loop Output Impedance AC Distortion Total Harmonic Distortion plus Noise Step Response Rise Time, 10% to 90% Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density
Sym
GBWP PM ROUT THD+N
Min
-- -- -- --
Typ
20 60 15 0.0018
Max
-- -- -- --
Units
MHz % G = +1
Conditions
G = +1, VOUT = 2VP-P, f = 1 kHz, VDD = 5.5V, BW = 80 kHz G = +1, VOUT = 100 mVP-P G = +1 f = 0.1 Hz to 10 Hz f = 1 kHz
tr SR Eni eni ini
-- -- -- --
13 10 20 13 4
-- -- -- -- --
ns V/s VP-P fA/Hz
nV/Hz f = 1 MHz
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
CAL/CS Low Specifications CAL/CS Logic Threshold, Low Note 1: 2: 3:
Sym
Min
Typ
Max
Units
Conditions
VIL
VSS
--
0.2VDD
V
The MCP622 has its CAL/CS input internally pulled down to VSS (0V). This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised before the calibration is complete, the calibration will be aborted and the part will return to low power mode. For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously (within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled.
DS22188A-page 4
(c) 2009 Microchip Technology Inc.
MCP621/2/5
DIGITAL ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
CAL/CS Input Current, Low CAL/CS High Specifications CAL/CS Logic Threshold, High CAL/CS Input Current, High GND Current
Sym
ICSL VIH ICSH ISS ISS ISS ISS
Min
--
Typ
0
Max
--
Units
nA CAL/CS = 0V
Conditions
0.8VDD -- -3.5 -8 -5 -10 -- -- -- 100 0.7 -1.8 -4 -2.5 -5 5 50 200 200
VDD -- -- -- -- -- -- -- -- 300
V A A A A A M nA ns ms CAL/CS = VDD, TA = 125C G = +1 V/V, VL = VSS, VDD = 2.5V to 0V step to VOUT = 0.1 (2.5V) G = +1 V/V, VL = VSS, VDD = 0V to 2.5V step to VOUT = 0.9 (2.5V) CAL/CS = VDD Single, CAL/CS = VDD = 2.5V Single, CAL/CS = VDD = 5.5V Dual, CAL/CS = VDD = 2.5V Dual, CAL/CS = VDD = 5.5V
CAL/CS Internal Pull Down Resistor Amplifier Output Leakage POR Dynamic Specifications VDD Low to Amplifier Off Time (output goes High-Z) VDD High to Amplifier On Time (including calibration) CAL/CS Dynamic Specifications CAL/CS Input Hysteresis CAL/CS Setup Time (between CAL/CS edges) CAL/CS High to Amplifier Off Time (output goes High-Z) CAL/CS Low to Amplifier On Time (including calibration) Note 1: 2: 3:
RPD IO(LEAK) tPOFF tPON
VHYST tCSU tCOFF tCON
-- 1 -- --
0.25 -- 200 5
-- -- -- 8
V s ns ms G = +1 V/V, VL = VSS (Notes 2, 3) CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2) G = +1 V/V, VL = VSS, CAL/CS = 0.8VDD to VOUT = 0.1 (VDD/2) G = +1 V/V, VL = VSS, CAL/CS = 0.2VDD to VOUT = 0.9 (VDD/2)
The MCP622 has its CAL/CS input internally pulled down to VSS (0V). This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised before the calibration is complete, the calibration will be aborted and the part will return to low power mode. For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously (within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-3x3 DFN Thermal Resistance, 8L-SOIC Thermal Resistance, 10L-3x3 DFN Thermal Resistance, 10L-MSOP Note 1: 2:
Sym
TA TA TA JA JA JA JA
Min
-40 -40 -65 -- -- -- --
Typ
-- -- -- 60 140.9 57 202
Max
+125 +125 +150 -- -- -- --
Units
C C C C/W C/W C/W C/W (Note 2) (Note 2) (Note 1)
Conditions
Operation must not cause TJ to exceed Maximum Junction Temperature specification (150C). Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
(c) 2009 Microchip Technology Inc.
DS22188A-page 5
MCP621/2/5
1.3 Timing Diagram
VIH VPRH tPON VOUT High-Z ISS -3 A (typical) ICS 0 nA (typical) On -2.5 mA (typical) tCOFF High-Z tCSU VIL VPRL tCON On -2.5 mA (typical) tPOFF High-Z
CAL/CS VDD
-3 A (typical) 0.7 A (typical)
-3 A (typical) 0 nA (typical)
FIGURE 1-1:
Timing Diagram.
1.4
Test Circuits
CF 6.8 pF RG 10 k VP VIN+ MCP62X VIN- VM RG 10 k RF 10 k CF 6.8 pF RL 2 k VOUT CL 50 pF CB1 100 nF RF 10 k VDD
The circuit used for most DC and AC tests is shown in Figure 1-2. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit's common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL.
VDD/2
EQUATION 1-1:
G DM = R F R G V CM = ( V P + V DD 2 ) 2
CB2 2.2 F
V OUT = ( V DD 2 ) + ( V P - V M ) + V OST ( 1 + G DM ) Where: GDM = Differential Mode Gain VCM = Op Amp's Common Mode Input Voltage VOST = Op Amp's Total Input Offset Voltage (V/V) (V) (mV)
V OST = V IN- - V IN+
VL
FIGURE 1-2: AC and DC Test Circuit for Most Specifications.
DS22188A-page 6
(c) 2009 Microchip Technology Inc.
MCP621/2/5
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.1
22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Percentage of Occurrences
DC Signal Inputs
80 Samples TA = +25C VDD = 2.5V and 5.5V Calibrated at +25C
300 200 100 0 -100 -200 -300 -400 -500 -600 -700
Input Offset Voltage (V)
Representative Part Calibrated at VDD = 6.5V +125C +85C +25C -40C
-80
-60
-40 -20 0 20 40 Input Offset Voltage (V)
60
80
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage.
50 40 30 20 10 0 -10 -20 -30 -40 -50
Representative Part
24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0%
Percentage of Occurrences
Input Offset Voltage (V)
80 Samples VDD = 2.5V and 5.5V TA = -40C to +125C Calibrated at +25C
VDD = 5.5V
VDD = 2.5V
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (V/C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5: Output Voltage.
0.0 Low Input Common Mode Headroom (V) -0.1 -0.2 -0.3
Input Offset Voltage vs.
50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0%
Percentage of Occurrences
200 Samples TA = +25C VDD = 2.5V and 5.5V
1 Lot Low (VCMR_L - VSS)
No Change (includes noise) Calibration Changed (-1 step) Calibration Changed (+1 step)
VDD = 2.5V
VDD = 5.5V
-0.4 -0.5 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 Input Offset Voltage Calibration Repeatability (V)
FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration).
FIGURE 2-6: Low Input Common Mode Voltage Headroom vs. Ambient Temperature.
(c) 2009 Microchip Technology Inc.
DS22188A-page 7
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
1.4 High Input Common Mode Headroom (V)
110 105 100 95 90 85 80 75 70 65 60 -50 -25
1 Lot High (VDD - VCMR_H)
CMRR, PSRR (dB)
1.3
VDD = 2.5V
PSRR CMRR, VDD = 5.5V CMRR, VDD = 2.5V
1.2
1.1
VDD = 5.5V
1.0 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-7: High Input Common Mode Voltage Headroom vs. Ambient Temperature.
1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.6
FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature.
130 DC Open-Loop Gain (dB) 125 120 115 110 105 100 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 2.5V VDD = 5.5V
Input Offset Voltage (V)
VDD = 2.5V Representative Part
+125C +85C +25C -40C
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Input Common Mode Voltage (V)
FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V.
1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5
VDD = 5.5V Representative Part
2.0
FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature.
10,000 Input Bias, Offset Currents (pA)
Input Offset Voltage (V)
VDD = 5.5V VCM = VCMR_H
1,000
IB
100
+125C +85C +25C -40C
10
| IOS |
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1 25 45 65 85 105 Ambient Temperature (C) 125
Input Common Mode Voltage (V)
FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.
FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.
DS22188A-page 8
(c) 2009 Microchip Technology Inc.
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
120 Input Bias, Offset Currents (pA) 100 80 60 40 20 0 -20 -40 -60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.5 Common Mode Input Voltage (V) 6.0
IB Representative Part TA = +85C VDD = 5.5V IOS
1.E-03 1m Input Current Magnitude (A) 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11
+125C +85C +25C -40C
1p 1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.
1500 Input Bias, Offset Currents (pA) 1000 500 0
IB Representative Part TA = +125C VDD = 5.5V IOS
FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS).
-500 -1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V)
FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.
(c) 2009 Microchip Technology Inc.
DS22188A-page 9
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.2
Other DC Voltages and Currents
14 12 10 8 6 4 2 0 1 10 Output Current Magnitude (mA) 100
VDD = 2.5V VDD - VOH IOUT
Ratio of Output Headroom to Output Current (mV/mA)
VDD = 5.5V
3.5
VOL - VSS -IOUT
3.0 Supply Current (mA/amplifier) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 6.0 5.0 Power Supply Voltage (V) 6.5 125 5.5
+125C +85C +25C -40C
FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current.
20 18 16 14 12 10 8 6 4 2 0
FIGURE 2-19: Supply Voltage.
3.0 2.5 Supply Current (mA/amplifier) 2.0 1.5 1.0 0.5
VDD = 2.5V
Supply Current vs. Power
RL = 2 k
VDD = 5.5V
VOL - VSS
Output Headroom (mV)
VDD = 5.5V
VDD = 2.5V
VDD - VOH
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VPRH VPRL
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
Common Mode Input Voltage (V)
FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature.
100 80 60 40 20 0 -20 -40 -60 -80 -100 0.0 0.5 1.0 1.5 2.0 2.5
FIGURE 2-20: Supply Current vs. Common Mode Input Voltage.
1.8 POR Trip Voltages (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Ambient Temperature (C)
Output Short Circuit Current (mA)
+125C +85C +25C -40C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Supply Voltage (V)
6.5
FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage.
FIGURE 2-21: Power On Reset Voltages vs. Ambient Temperature.
DS22188A-page 10
(c) 2009 Microchip Technology Inc.
4.5
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
Percentage of Occurrences 30% 25% 20% 15% 10% 5% 0% 33.20% 33.24% 33.28% 33.32% 33.36% 33.40% 33.44% 33.48% 33.52% 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
Normalized Internal Calibration Voltage; VCAL/VDD
FIGURE 2-22: Normalized Internal Calibration Voltage.
FIGURE 2-23: Temperature.
Internal V CAL Resistance (k)
144 Samples VDD = 2.5V and 5.5V
VCAL Input Resistance vs.
(c) 2009 Microchip Technology Inc.
DS22188A-page 11
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.3
100
Frequency Response
45 Gain Bandwidth Product (MHz) 40 35 30 25 20 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1k 1.E+3 10k 100k 1.E+4 1.E+5 Frequency (Hz) 1M 1.E+6 10M 1.E+7 -0.5 Common Mode Input Voltage (V) 6.0 70 65
PM GBWP PM
70 65 60
VDD = 5.5V VDD = 2.5V
90 CMRR, PSRR (dB) 80 70 60 50 40 30 20 10 100 1.E+2
PSRR+ PSRRCMRR
55 50 45 40
FIGURE 2-24: Frequency.
CMRR and PSRR vs.
FIGURE 2-27: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.
45 Gain Bandwidth Product (MHz) Open-Loop Phase () 40 35 30 25 20 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
GBWP
140 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20
| AOL | AOL
0 -30 -60 -90 -120 -150 -180 -210 -240
60
VDD = 5.5V VDD = 2.5V
55 50 45 40
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 100k 1.E+6 10M 100M 1 10 100 1k 10k 1.E+5 1M 1.E+7 1.E+8
Frequency (Hz)
FIGURE 2-25: Frequency.
45 Gain Bandwidth Product (MHz) 40 35 30 25 20 15 -50 -25
PM
Open-Loop Gain vs.
FIGURE 2-28: Gain Bandwidth Product and Phase Margin vs. Output Voltage.
Open-Loop Output Impedance ()
70 65 60 55 Phase Margin ()
100
10
G = 101 V/V G = 11 V/V G = 1 V/V
VDD = 5.5V VDD = 2.5V
GBWP
50 45 40 125
1
0 25 50 75 100 Ambient Temperature (C)
0.1 1k 10k 100k 1M 10M 100M 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz)
FIGURE 2-26: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency.
DS22188A-page 12
(c) 2009 Microchip Technology Inc.
Phase Margin ()
Phase Margin ()
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
10 9 8 7 6 5 4 3 2 1 0 10p 1.0E-11
150 140 Channel-to-Channel Separation (dB) 130 120 110 100 90 80 70 60
RS = 10 k RS = 100 k
RS = 0 RS = 1 k
Gain Peaking (dB)
RTI VCM = VDD/2 G = +1 V/V
GN = 1 V/V GN = 2 V/V GN 4 V/V
100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F)
50 1k 1.E+03
10k 1.E+04
1M 100k 1.E+05 1.E+06 Frequency (Hz)
10M 1.E+07
FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load.
FIGURE 2-31: Channel-to-Channel Separation vs. Frequency.
(c) 2009 Microchip Technology Inc.
DS22188A-page 13
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.4
Input Noise Voltage Density (nV/Hz)
1.E+4 10
Input Noise and Distortion
20 Input Offset + Noise; V OS + eni(t) (V) 15 10 5 0 -5 -10 -15 -20 0 5 10 15 20 25 30 Time (min) 35 40 45
Representative Part Analog NPBW = 0.1 Hz Sample Rate = 2 SPS
1 1.E+3
1.E+2 100n
10n 1.E+1 0.1 1.E-1
1 1.E+0
10 1.E+1
100 1.E+2
1k 10k 1.E+5 1M 10M 1.E+3 1.E+4 100k 1.E+6 1.E+7 Frequency (Hz)
FIGURE 2-32: vs. Frequency.
300 250 200 150 100 50 0 -0.5
f = 100 Hz
Input Noise Voltage Density
FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter.
1
Input Noise Voltage Density (nV/Hz)
THD + Noise (%)
0.1
BW = 22 Hz to > 500 kHz
VDD = 2.5V VDD = 5.5V
G = 1 V/V G = 11 V/V
0.01
0.001
BW = 22 Hz to 80 kHz
VDD = 5.0V VOUT = 2 VP-P
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.0001 100 1.E+2
1k 1.E+3
Common Mode Input Voltage (V)
10k 1.E+4 Frequency (Hz)
100k 1.E+5
FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz.
30 25 20 15 10 5 0 -0.5
f = 1 MHz VDD = 2.5V VDD = 5.5V
FIGURE 2-36:
THD+N vs. Frequency.
Input Noise Voltage Density (nV/Hz)
0.5
3.0
Common Mode Input Voltage (V)
FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz.
5.5
0.0
1.0
1.5
2.5
3.5
4.0
5.0
2.0
4.5
DS22188A-page 14
(c) 2009 Microchip Technology Inc.
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.5
Time Response
VDD = 5.5V G=1
VIN
VOUT
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Output Voltage (10 mV/div)
Output Voltage (V)
VDD = 5.5V G = -1 RF = 1 k
VIN
VOUT
0
20
40
60
80 100 120 140 160 180 200 Time (ns)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (s)
FIGURE 2-37: Step Response.
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
VDD = 5.5V G=1
Non-inverting Small Signal
FIGURE 2-40: Response.
7 Input, Output Voltages (V) 6 5 4 3 2 1 0 -1 0 1 2 3
VDD = 5.5V G=2
Inverting Large Signal Step
VIN VOUT
Output Voltage (V)
VIN
VOUT
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (s)
4 5 6 Time (ms)
7
8
9
10
FIGURE 2-38: Step Response.
Non-inverting Large Signal
FIGURE 2-41: The MCP621/2/5 Family Shows No Input Phase Reversal with Overdrive.
24 22 20 18 16 14 12 10 8 6 4 2 0
Falling Edge
Output Voltage (10 mV/div)
VIN
VDD = 5.5V G = -1 RF = 1 k
Slew Rate (V/s)
VDD = 2.5V
VDD = 5.5V Rising
VOUT
0
100
200
300
400 500 Time (ns)
600
700
800
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-39: Response.
Inverting Small Signal Step
FIGURE 2-42: Temperature.
Slew Rate vs. Ambient
(c) 2009 Microchip Technology Inc.
DS22188A-page 15
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
10 Maximum Output Voltage Swing (VP-P)
VDD = 5.5V VDD = 2.5V
1
0.1 100k 1.E+05
1M 10M 1.E+06 1.E+07 Frequency (Hz)
100M 1.E+08
FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency.
DS22188A-page 16
(c) 2009 Microchip Technology Inc.
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
2.6
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
Calibration and Chip Select Response
CAL/CS = VDD
0.40 CAL/CS Hysteresis (V) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 5.5V VDD = 2.5V
CAL/CS Current (A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
FIGURE 2-44: Supply Voltage.
8 7 6 5 CAL/CS, V OUT (V) 4 3 2 1 0 -1 0 2 4
Calibration starts CAL/CS VOUT IDD
CAL/CS Current vs. Power
FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature.
8 CAL/CS Turn On Time (ms) 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 2.5V G=1 VL = 0V
4 2 0 -2 -4 -6 -8 -10 -12
Op Amp Op Amp turns on turns off
6 8 10 Time (ms)
12
14
16
FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V.
Power Supply Current; IDD (mA) 16 14 12 10 CAL/CS, V OUT (V) 8 6 4 2 0 -2 0 2 4 6 8 10 Time (ms) 12 14 16
Calibration starts CAL/CS VOUT Op Amp Op Amp turns on turns off IDD
VDD = 5.5V G=1 VL = 0V
Power Supply Current; IDD (mA)
6
FIGURE 2-48: CAL/CS Turn On Time vs. Ambient Temperature.
6 4 2 0 -2 -4 -6 -8 -10 -12
8 CAL/CS Pull-down Resistor (M) 7 6 5 4 3 2 1 0 -50 -25
Representative Part
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V.
FIGURE 2-49: CAL/CS's Pull-down Resistor (RPD) vs. Ambient Temperature.
(c) 2009 Microchip Technology Inc.
DS22188A-page 17
MCP621/2/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF, and CAL/CS = VSS.
0 Negative Power Supply Current; I SS (A) -1 -2 -3 -4 -5 -6 -7 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V)
+125C +85C +25C -40C
Output Leakage Current (A)
CAL/CS = VDD
1.E-06 1.E-07 1.E-08 1.E-09 1.E-10
CAL/CS = VDD = 5.5V
+125C +85C
+25C
1.E-11 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V)
FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage.
FIGURE 2-51: Output Voltage.
Output Leakage Current vs.
DS22188A-page 18
(c) 2009 Microchip Technology Inc.
MCP621/2/5
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP621 SOIC 6 2 3 4 8 -- -- -- -- 7 5 1 --
PIN FUNCTION TABLE
MCP622 MCP625 MSOP 1 2 3 4 5 6 7 8 9 10 -- -- -- DFN 1 2 3 4 5 6 7 8 9 10 -- -- 11 DFN 1 2 3 4 -- -- 5 6 7 8 -- -- 9 Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VSS CAL/CS, CALA/CSA CALB/CSB VINB+ VINB- VOUTB VDD VCAL NC EP Description Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Negative Power Supply Calibrate/Chip Select Digital Input (op amp A) Calibrate/Chip Select Digital Input (op amp B) Non-inverting Input (op amp B) Inverting Input (op amp B) Output (op amp B) Positive Power Supply Calibration Common Mode Voltage Input No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS
SOIC 1 2 3 4 -- -- 5 6 7 8 -- -- --
3.1
Analog Outputs
3.5
Calibrate/Chip Select Digital Input
The analog output pins (VOUT) are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN-, ...) are high-impedance CMOS inputs with low bias currents.
This input (CAL/CS, ...) is a CMOS, Schmitt-triggered input that affects the calibration and low power modes of operation. When this pin goes high, the part is placed into a low power mode and the output is high-Z. When this pin goes low, a calibration sequence is started (which corrects VOS). At the end of the calibration sequence, the output becomes low impedance and the part resumes normal operation. An internal POR triggers a calibration event when the part is powered on, or when the supply voltage drops too low. Thus, the MCP622 parts are calibrated, even though they do not have a CAL/CS pin.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors.
3.6
Exposed Thermal Pad (EP)
3.4
Calibration Common Mode Voltage Input
There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA).
A low impedance voltage placed at this input (VCAL) analog input will set the op amps' common mode input voltage during calibration. If this pin is left open, the common mode input voltage during calibration is approximately VDD/3. The internal resistor divider is disconnected from the supplies whenever the part is not in calibration.
(c) 2009 Microchip Technology Inc.
DS22188A-page 19
MCP621/2/5
NOTES:
DS22188A-page 20
(c) 2009 Microchip Technology Inc.
MCP621/2/5
4.0 APPLICATIONS
4.1.3 INTERNAL POR
The MCP621/2/5 family of self-zeroed op amps is manufactured using Microchip's state of the art CMOS process. It is designed for low cost, low power and high precision applications. Its low supply voltage, low quiescent current and wide bandwidth makes the MCP621/2/5 ideal for battery-powered applications. This part includes an internal Power On Reset (POR) to protect the internal calibration memory cells. The POR monitors the power supply voltage (VDD). When the POR detects a low VDD event, it places the part into the low power mode of operation. When the POR detects a normal VDD event, it starts a delay counter, then triggers an calibration event. The additional delay gives a total POR turn on time of 200 ms (typical); this is also the power up time (since the POR is triggered at power up).
4.1
Calibration and Chip Select
These op amps include circuitry for dynamic calibration of the offset voltage (VOS).
4.1.4
PARITY DETECTOR
4.1.1
mCal CALIBRATION CIRCUITRY
The internal mCal circuitry, when activated, starts a delay timer (to wait for the op amp to settle to its new bias point), then calibrates the input offset voltage (VOS). The mCal circuitry is triggered at power-up (and after some power brown out events) by the internal POR, and by the memory's Parity Detector. The power up time, when the mCal circuitry triggers the calibration sequence, is 200 ms (typical).
A parity error detector monitors the memory contents for any corruption. In the rare event that a parity error is detected (e.g., corruption from an alpha particle), a POR event is automatically triggered. This will cause the input offset voltage to be re-corrected, and the op amp will not return to normal operation for a period of time (the POR turn on time, tPON).
4.1.5
CALIBRATION INPUT PIN
4.1.2
CAL/CS PIN
The CAL/CS pin gives the user a means to externally demand a low power mode of operation, then to calibrate VOS. Using the CAL/CS pin makes it possible to correct VOS as it drifts over time (1/f noise and aging; see Figure 2-35) and across temperature. The CAL/CS pin performs two functions: it places the op amp(s) in a low power mode when it is held high, and starts a calibration event (correction of VOS) after a rising edge. While in the low power mode, the quiescent current is quite small (ISS = -3 A, typical). The output is also is in a High-Z state. During the calibration event, the quiescent current is near, but smaller than, the specified quiescent current (6 mA, typical). The output continues in the High-Z state, and the inputs are disconnected from the external circuit, to prevent internal signals from affecting circuit operation. The op amp inputs are internally connected to a common mode voltage buffer and feedback resistors. The offset is corrected (using a digital state machine, logic and memory), and the calibration constants are stored in memory. Once the calibration event is completed, the amplifier is reconnected to the external circuitry. The turn on time, when calibration is started with the CAL/CS pin, is 5 ms (typical). There is an internal 5 M pull-down resistor tied to the CAL/CS pin. If the CAL/CS pin is left floating, the amplifier operates normally.
A VCAL pin is available in some options (e.g., the single MCP621) for those applications that need the calibration to occur at an internally driven common mode voltage other than VDD/3. Figure 4-1 shows the reference circuit that internally sets the op amp's common mode reference voltage (VCM_INT) during calibration (the resistors are disconnected from the supplies at other times). The 5 k resistor provides over-current protection for the buffer. VDD 300 k VCAL 150 k VSS To op amp during calibration 5 k BUFFER VCM_INT
FIGURE 4-1: Input Circuitry.
Common-Mode Reference's
When the VCAL pin is left open, the internal resistor divider generates a VCM_INT of approximately VDD/3, which is near the center of the input common mode voltage range. It is recommended that an external capacitor from VCAL to ground be added to improve noise immunity.
(c) 2009 Microchip Technology Inc.
DS22188A-page 21
MCP621/2/5
When the VCAL pin is driven by an external voltage source, which is within its specified range, the op amp will have its input offset voltage calibrated at that common mode input voltage. Make sure that VCAL is within its specified range. It is possible to use an external resistor voltage divider to modify VCM_INT; see Figure 4-2. The internal circuitry at the VCAL pin looks like 100 k tied to VDD/3. The parallel equivalent of R1 and R2 should be much smaller than 100 k to minimize differences in matching and temperature drift between the internal and external resistors. Again, make sure that VCAL is within its specified range. VDD MCP62X R1 C1 R2 VSS VCAL VDD Bond Pad
VIN+ Bond Pad
Input Stage
Bond V - IN Pad
VSS Bond Pad
FIGURE 4-3: Structures.
Simplified Analog Input ESD
FIGURE 4-2: Resistors.
Setting VCM with External
In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Section 1.1 "Absolute Maximum Ratings "). Figure 4-4 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 R1 D2 MCP62X VOUT R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 >
For instance, a design goal to set VCM_INT = 0.1V when VDD = 2.5V could be met with: R1 = 24.3 k, R2 = 1.00 k and C1 = 100 nF. This will keep VCAL within its range for any VDD, and should be close enough to 0V for ground based applications.
4.2
4.2.1
Input
PHASE REVERSAL
V1 V2
The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-41 shows an input voltage exceeding both supplies with no phase inversion.
4.2.2
INPUT VOLTAGE AND CURRENT LIMITS
FIGURE 4-4: Inputs.
Protecting the Analog
The ESD protection on the inputs can be depicted as shown in Figure 4-3. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits.
It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-15. Applications that are high impedance may need to limit the usable voltage range.
DS22188A-page 22
(c) 2009 Microchip Technology Inc.
MCP621/2/5
4.2.3 NORMAL OPERATION 4.3.2.1 Power Dissipation
The input stage of the MCP621/2/5 op amps uses a differential PMOS input stage. It operates at low common mode input voltage (VCM), with VCM up to VDD - 1.3V and down to VSS - 0.3V. The input offset voltage (VOS) is measured at VCM = VSS - 0.3V and VDD - 1.3V to ensure proper operation. See Figure 2-6 and Figure 2-7 for temperature effects. When operating at very low non-inverting gains, the output voltage is limited at the top by the VCM range (< VDD - 1.3V); see Figure 4-5. VDD VIN MCP62X VOUT MCP62X ISS VSS VL RL Since the output short circuit current (ISC) is specified at 70 mA (typical), these op amps are capable of both delivering and dissipating significant power. Two common loads, and their impact on the op amp's power dissipation, will be discussed. Figure 4-7 shows a resistive load (RL) with a DC output voltage (VOUT). VL is RL's ground point, VSS is usually ground (0V) and IOUT is the output current. The input currents are assumed to be negligible. VDD IDD IOUT VOUT
V SS < V IN, V OUT V DD - 1.3V
FIGURE 4-5: Unity Gain Voltage Limitations for Linear Operation.
FIGURE 4-7: Diagram for Resistive Load Power Calculations.
The DC currents are:
4.3
4.3.1
Rail-to-Rail Output
MAXIMUM OUTPUT VOLTAGE
The Maximum Output Voltage (see Figure 2-16 and Figure 2-17) describes the output range for a given load. For instance, the output voltage swings to within 40 mV of the negative rail with a 2 k load tied to VDD/2.
EQUATION 4-1:
V OUT - V L I OUT = ------------------------RL I DD I Q + max ( 0, I OUT ) I SS - I Q + min ( 0, I OUT ) Where: IQ = Quiescent supply current for one op amp (mA/amplifier) VOUT = A DC value (V) The DC op amp power is:
4.3.2
OUTPUT CURRENT
Figure 4-6 shows the possible combinations of output voltage (VOUT) and output current (IOUT). IOUT is positive when it flows out of the op amp into the external circuit.
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5
VOH Limited (VDD = 5.5V) RL = 2 k RL = 100 RL = 10
EQUATION 4-2:
+ISC Limited
VOUT (V)
-ISC Limited
P OA = I DD ( V DD - V OUT ) + I SS ( V SS - V OUT ) The maximum op amp power, for resistive loads at DC, occurs when VOUT is halfway between VDD and VL or halfway between VSS and VL:
80
VOL Limited
-80
-60
-40
-20
20
40
IOUT (mA)
60
EQUATION 4-3:
max ( P OA ) = I DD ( V DD - V SS ) max ( V DD - V L, V L - V SS ) + ----------------------------------------------------------------4R L
2
FIGURE 4-6:
Output Current.
(c) 2009 Microchip Technology Inc.
0
DS22188A-page 23
MCP621/2/5
Figure 4-7 shows a capacitive load (CL), which is driven by a sine wave with DC offset. The capacitive load causes the op amp to output higher currents at higher frequencies. Because the output rectifies IOUT, the op amp's dissipated power increases (even though the capacitor does not dissipate power). VDD IDD MCP62X ISS VSS CL IOUT VOUT The power dissipated in a package depends on the powers dissipated by each op amp in that package:
EQUATION 4-7:
n
P PKG = Where:
POA
k=1
n = Number of op amps in package (1 or 2) The maximum ambient to junction temperature rise (TJA) and junction temperature (TJ) can be calculated using the maximum expected package power (PPKG), ambient temperature (TA) and the package thermal resistance (JA) found in Section "Temperature Specifications":
FIGURE 4-8: Diagram for Capacitive Load Power Calculations.
The output voltage is assumed to be:
EQUATION 4-8:
T JA = P PKG JA
T J = T A + T JA The worst case power de-rating for the op amps in a particular package can be easily calculated:
EQUATION 4-4:
V OUT = V DC + V AC sin ( t ) Where: VDC = DC offset (V) VAC = Peak output swing (VPK)
EQUATION 4-9:
T Jmax - T A P PKG --------------------------
= Radian frequency (2 f) (rad/s)
The op amp's currents are: Where:
JA
EQUATION 4-5:
dV OUT I OUT = C L ---------------- = V AC C L cos ( t ) dt I DD I Q + max ( 0, I OUT ) Where: IQ = Quiescent supply current for one op amp (mA/amplifier) The op amp's instantaneous power, average power and peak power are: I SS - I Q + min ( 0, I OUT )
TJmax = Absolute maximum junction temperature (C) TA = Ambient temperature (C) Several techniques are available to reduce TJA for a given package: * Reduce JA - Use another package - Improve the PCB layout (ground plane, etc.) - Add heat sinks and air flow * Reduce max(PPKG) - Increase RL - Decrease CL - Limit IOUT using RISO (see Figure 4-9) - Decrease VDD
EQUATION 4-6:
P OA = I DD ( V DD - V OUT ) + I SS ( V SS - V OUT ) 4V AC fC L ave ( P OA ) = ( V DD - V SS ) I Q + ----------------------- -
max ( P OA ) = ( V DD - V SS ) ( I Q + 2V AC fC L )
DS22188A-page 24
(c) 2009 Microchip Technology Inc.
MCP621/2/5
4.4
4.4.1
Improving Stability
CAPACITIVE LOADS
4.4.2
GAIN PEAKING
Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. See Figure 2-30. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 10 pF when G = +1), a small series resistor at the output (RISO in Figure 4-9) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG RF RISO VOUT CL RN MCP62X
Figure 4-11 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp's common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel.
VP VM
RN
CN
MCP62X VOUT
RG
CG
RF
FIGURE 4-11: Capacitance.
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF. CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2RNCN). The largest value of RF that should be used depends on noise gain (see GN in Section 4.4.1 "Capacitive Loads") and CG. Figure 4-12 shows the maximum recommended RF for several CG values.
1.E+05 100k Maximum Recommended RF ()
CG = 10 pF CG = 32 pF CG = 100 pF CG = 320 pF CG = 1 nF
FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads.
Figure 4-10 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
1,000 Recommended RISO ()
10k 1.E+04
100
1k 1.E+03
10
GN = +1 GN +2
GN > +1 V/V
100 1.E+02 1 10 Noise Gain; GN (V/V) 100
1 1p 1.E-12
10p 100p 1n 1.E-11 1.E-10 1.E-09 Normalized Capacitance; CL/GN (F)
10n 1.E-08
FIGURE 4-12: RF vs. Gain.
Maximum Recommended
FIGURE 4-10: Recommended RISO Values for Capacitive Loads.
After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP621/2/5 SPICE macro model are helpful.
Figure 2-37 and Figure 2-38 show the small signal and large signal step responses at G = +1 V/V. The unity gain buffer usually has RF = 0 and RG open. Figure 2-39 and Figure 2-40 show the small signal and large signal step responses at G = -1 V/V. Since the noise gain is 2 V/V and CG 10 pF, the resistors were chosen to be RF = RG = 1k and RN = 500.
(c) 2009 Microchip Technology Inc.
DS22188A-page 25
MCP621/2/5
It is also possible to add a capacitor (CF) in parallel with RF to compensate for the de-stabilizing effect of CG. This makes it possible to use larger values of RF. The conditions for stability are summarized in Equation 4-10. Use coax cables, or low inductance wiring, to route signal and power to and from the PCB. Mutual and self inductance of power wires is often a cause of crosstalk and unusual behavior.
EQUATION 4-10:
Given: G N1 = 1 + R F R G
4.7
4.7.1
Typical Applications
POWER DRIVER WITH HIGH GAIN
G N2 = 1 + C G C F f Z = f F ( G N1 G N2 ) f F = 1 ( 2R F C F )
We need: f F f GBWP ( 2G N2 ) , G N1 < G N2 f F f GBWP ( 4G N1 ) , G N1 > G N2
Figure 4-13 shows a power driver with high gain (1 + R2/R1). The MCP621/2/5 op amp's short circuit current makes it possible to drive significant loads. The calibrated input offset voltage supports accurate response at high gains. R3 should be small, and equal to R1||R2, in order to minimize the bias current induced offset. R1 R3 VIN MCP62X R2
VDD/2
VOUT RL
4.5
Power Supply
With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used. These op amps require a bulk capacitor (i.e., 2.2 F or larger) within 50 mm to provide large, slow currents. Tantalum capacitors, or their equivalent, may be a good choice. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem.
FIGURE 4-13: 4.7.2
Power Driver.
OPTICAL DETECTOR AMPLIFIER
4.6
High Speed PCB Layout
These op amps are fast enough that a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in performance. Good PC board layout techniques will help you achieve the performance shown in the specifications and Typical Performance Curves; it will also help you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane. Connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Separate digital from analog, low speed from high speed, and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals. Sometimes, it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect guard traces to ground plane at both ends, and in the middle for long traces.
Figure 4-14 shows a transimpedance amplifier, using the MCP621 op amp, in a photo detector circuit. The photo detector is a capacitive current source. The op amp's input common mode capacitance (9 pF, typical) and differential mode capacitance (2 pF, typical) act in parallel with CD. RF provides enough gain to produce 10 mV at VOUT. CF stabilizes the gain and limits the transimpedance bandwidth to about 0.51 MHz. RF's parasitic capacitance (e.g., 0.15 pF for a 0603 SMD) acts in parallel with CF. CF 3 pF Photo Detector ID 100 nA CD 30pF MCP621 VDD/2 RF 100 k
VOUT
FIGURE 4-14: Transimpedance Amplifier for an Optical Detector.
DS22188A-page 26
(c) 2009 Microchip Technology Inc.
MCP621/2/5
4.7.3 H-BRIDGE DRIVER
Figure 4-15 shows the MCP622 dual op amp used as a H-bridge driver. The load could be a speaker or a DC motor. 1/2 MCP622
VIN
RF RGT RGB
RF
VOT RL
RF
VOB
VDD/2
1/2 MCP622
FIGURE 4-15:
H-Bridge Driver.
This circuit automatically makes the noise gains (GN) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). Equation 4-11 shows how to calculate RGT and RGB so that both op amps have the same DC gains; GDM needs to be selected first.
EQUATION 4-11:
V OT - V OB G DM -------------------------------- 2 V/V V IN - V DD 2 RF R GT = -------------------------------( G DM 2 ) - 1 RF R GB = -----------------G DM 2 Equation 4-12 gives the resulting common mode and differential mode output voltages.
EQUATION 4-12:
V OT + V OB V DD -------------------------- = ---------2 2 V DD V OT - V OB = G DM V IN - ---------- 2
(c) 2009 Microchip Technology Inc.
DS22188A-page 27
MCP621/2/5
NOTES:
DS22188A-page 28
(c) 2009 Microchip Technology Inc.
MCP621/2/5
5.0 DESIGN AIDS
5.5
Microchip provides the basic design aids needed for the MCP621/2/5 family of op amps.
Analog Demonstration and Evaluation Boards
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP621/2/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. Some boards that are especially useful are: * * * * * * MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV
5.2
FilterLab(R) Software
Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1177: "Op Amp Precision Design: DC Errors", DS01177 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 Some of these application notes, and others, are listed in the design guide: * "Signal Chain Design Guide", DS21825
5.3
MindiTM Circuit Designer & Simulator
Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation.
5.4
Microchip Advanced Part Selector (MAPS)
MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts.
(c) 2009 Microchip Technology Inc.
DS22188A-page 29
MCP621/2/5
NOTES:
DS22188A-page 30
(c) 2009 Microchip Technology Inc.
MCP621/2/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (3x3) (MCP622)
Device MCP622 Code DABL
Example:
XXXX YYWW NNN
Note: Applies to 8-Lead 3x3 DFN
DABL 0921 256
8-Lead SOIC (150 mil) (MCP621, MCP622) XXXXXXXX XXXXYYWW NNN
Example:
MCP621E SN e3 0921 256
10-Lead DFN (3x3) (MCP625)
Example:
Code BAFA
XXXX YYWW NNN
Device MCP625
Note: Applies to 10-Lead 3x3 DFN
BAFA 0921 256
10-Lead MSOP (MCP625)
Example:
XXXXXX YWWNNN
625EUN 921256
Legend: XX...X Y YY WW NNN * Note:
e3
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
DS22188A-page 31
MCP621/2/5
/HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 0) [ [
1RWH
PP %RG\ >')1@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
D N e N L EXPOSED PAD E K E2
b
NOTE 1
1
2 D2 TOP VIEW
2
1
NOTE 1
BOTTOM VIEW
A NOTE 2 A3 A1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 6WDQGRII &RQWDFW 7KLFNQHVV 2YHUDOO /HQJWK ([SRVHG 3DG :LGWK 2YHUDOO :LGWK ([SRVHG 3DG /HQJWK &RQWDFW :LGWK &RQWDFW /HQJWK 1 H $ $ $ ' ( ( ' E / 5() %6& %6& %6& 0,1 0,//,0(7(56 120 0$;
&RQWDFW WR ([SRVHG 3DG . 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 3DFNDJH PD\ KDYH RQH RU PRUH H[SRVHG WLH EDUV DW HQGV 3DFNDJH LV VDZ VLQJXODWHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &
%
DS22188A-page 32
(c) 2009 Microchip Technology Inc.
MCP621/2/5
/HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 0) [ [
1RWH
PP %RG\ >')1@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
(c) 2009 Microchip Technology Inc.
DS22188A-page 33
MCP621/2/5
/HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ
1RWH
PP %RG\ >62,&@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
D e N
E E1
NOTE 1 1 2 3 b h c h
A
A2
A1
L L1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1
0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$;
1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\
PP SHU VLGH
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &
%
DS22188A-page 34
(c) 2009 Microchip Technology Inc.
MCP621/2/5
/HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ
1RWH
PP %RG\ >62,&@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
(c) 2009 Microchip Technology Inc.
DS22188A-page 35
MCP621/2/5
/HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 0) [ [
1RWH
PP %RG\ >')1@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
D N e N L
b
E
K
E2
EXPOSED PAD NOTE 1 1 2 D2 TOP VIEW BOTTOM VIEW 2 1
NOTE 1
A
A3
A1
8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 6WDQGRII &RQWDFW 7KLFNQHVV 2YHUDOO /HQJWK ([SRVHG 3DG /HQJWK 2YHUDOO :LGWK ([SRVHG 3DG :LGWK &RQWDFW :LGWK &RQWDFW /HQJWK 1 H $ $ $ ' ' ( ( E /
NOTE 2
0,//,0(7(56 0,1 120 %6& 0$;
5() %6& %6&
&RQWDFW WR ([SRVHG 3DG . 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 3DFNDJH PD\ KDYH RQH RU PRUH H[SRVHG WLH EDUV DW HQGV 3DFNDJH LV VDZ VLQJXODWHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &
%
DS22188A-page 36
(c) 2009 Microchip Technology Inc.
MCP621/2/5
/HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 0) [ [
1RWH
PP %RG\ >')1@
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
(c) 2009 Microchip Technology Inc.
DS22188A-page 37
MCP621/2/5
/HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 81 >0623@
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
D N
E
E1
NOTE 1 1 b 2 e c
A
A2
L L1
8QLWV 0,//,0(7(56 0,1 120 %6& %6& %6& %6& 5() 0$;
A1
'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F
/HDG :LGWK E 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\
PP SHU VLGH
0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &
%
DS22188A-page 38
(c) 2009 Microchip Technology Inc.
MCP621/2/5
APPENDIX A: REVISION HISTORY
Revision A (June 2009)
* Original Release of this Document.
(c) 2009 Microchip Technology Inc.
DS22188A-page 39
MCP621/2/5
NOTES:
DS22188A-page 40
(c) 2009 Microchip Technology Inc.
MCP621/2/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range
MCP621: MCP621T: MCP622: MCP622T: MCP625: MCP625T:
/XX Package
Examples:
a) MCP621T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. Tape and Reel, Extended Temperature, 8LD DFN package. Tape and Reel, Extended Temperature, 8LD SOIC package. Tape and Reel, Extended Temperature, 10LD DFN package. Tape and Reel, Extended Temperature, 10LD MSOP package.
Device:
Single Op Amp Single Op Amp (Tape and Reel) (SOIC) Dual Op Amp Dual Op Amp (Tape and Reel) (DFN and SOIC) Dual Op Amp Dual Op Amp (Tape and Reel) (DFN and MSOP)
a) MCP622T-E/MF: b) MCP622T-E/SN:
a) MCP625T-E/MF: b) MCP625T-E/UN:
Temperature Range: E Package:
= -40C to +125C
MF = Plastic Dual Flat, No Lead (3x3 DFN), 8-lead, 10-lead SN = Plastic Small Outline, (3.90 mm), 8-lead UN = Plastic Micro Small Outline, (MSOP), 10-lead
(c) 2009 Microchip Technology Inc.
DS22188A-page 41
MCP621/2/5
NOTES:
DS22188A-page 42
(c) 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2009 Microchip Technology Inc.
DS22188A-page 43
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS22188A-page 44
(c) 2009 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of MCP621T-EMF

	To Download MCP621T-EMF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .